Instruction-Level Parallelism

不同于pipeline,parallelism需要额外的硬件资源 Instruction-Level Parallelism (ILP) Instruction-level parallelism: parallelism among instructions Pipelining is……

The Overview of Pipeline

Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory → register file → ALU → data memory → register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will……
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